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Shenmao Capacitors specialized in aluminum electrolytic capacitors from 1970

PCB layout when decoupling capacitor is put, be sure to pay attention!

by:Shenmao     2020-12-29
For the installation of the capacitance, first there is install the distance. Should the minimum value of capacitance, the highest resonance frequency and decoupling minimum radius, so in the most close to the position of the wafer. Capacitance values older can distance is farther, the outermost layer placed capacitance value maximum. However, all of the chip decoupling capacitors are close to the chip. The following figure is an example of a placement. 本例中的电容等级大致遵镶等级关系10倍。 One more thing to note that in place, it is best evenly distributed around the perimeter of the chip, for each capacity value level have to be like this. Usually chip was considered in the design of the power and ground pins are positioned, are generally distributed evenly in the four side of the wafer. Voltage disturbance, therefore, all around the chip, decoupling must also be evenly decoupling of the entire chip area. 680 of the above, if the pf capacitor is on the top of the wafer, due to the radius of decoupling problems, so can't for wafer lower voltage disturbance decoupling very well. 电容性安装在安装电容时,要从焊盘拉出一小段引出线,然后通过过孔和电源平面连接接地端用法相同。 这样韩流经电容性电流电路为:电源平面- ’过孔- ’提款权线- ’焊盘- ’电容- ’焊盘- ’提款权线- ’过孔- 'The ground plane, figure 2 intuitive shows the current return path. The first method: from the bonding pad long lead and then connected via, it will introduce a lot of parasitic inductance, must avoid doing so, this is the worst of the installation. 第二种方法:驻焊盘两个端点紧邻焊盘杆孔,比第二一种方法路面积小得多,寄生电感也较小,可以动作。 第三种方法:驻焊盘侧面杆孔,进一步减小了回路面积,寄生电感比第二种更小,是比较好的方法。 Fourth method: in the welding plate holes on both sides, compared to the third method, the equivalent capacitance each side is through via parallel connected to the power plane and ground plane, little more than a third type of parasitic inductance, as long as the space allows, as far as possible in this way. Finally a way: in the welding plate punching directly, parasitic inductance minimum, but the welding is likely appear problem, whether to use depends on the processing capability and the way. 推荐使用第三种和第四种方法。 需求一点:强调语句决定点工程师创建了节省空间,语句时谦让公共过度使用多枚电容孔,任什么情况下都不必要这样划分。 最后好想办法优化电容组合的设计,减少电容数量。
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